Theme 3: Devices & Circuits - Research Highlights

* “Specifically, Theme 3 explores ferroelectric gate stacks for 3D vertical NAND [1], ultra-low-leakage Amorphous Oxide Semiconductor (AOS) transistors for 3D DRAM [2], gain-cell embedded DRAM [3] and AOS Ferroelectric Field-Effect Transistors (FeFETs) [4] for SRAM augmentation, superlattice Phase-Change Memory (PCM) with reduced write energy [5], and a new sensing mechanism enabling ferroelectric non-volatile Capacitors (nvCap) [6].”

References: 

[1] H. J. Lee, M. Sohn, S. Yoo, Y. Lee, K. Kim, S.-G. Nam, Y. Park, S. Jo, D. Kim, J. Heo, W. Kim, D. Ha, A. I. Khan, S. Yu, D.-H. Choe, S. Datta, “Laminated ferroelectric stack for enhanced ISPP slope and endurance in FE-NAND,” IEEE Electron Device Letters, vol. 47, no. 1, pp. 188-191, 2026.
[2] K. Lee, S. Cho, P.-K. Hsu, J. Sharda, S. Datta, S. Yu, “Monolithically stackable 1T1C 3D DRAM: A technical survey,” IEEE Transactions on Electron Devices, vol. 73, no. 3, pp. 1092-1112, 2026.
[3] J. Sonawane, S. Deng, K. Lee, F. G. Waqar, C. Zhang, O. Phadke, S. Datta, S. Yu, “FAB gain cell memory: A folded asymmetric boosted design to improve sense margin for a refresh-free operation,” IEEE Symposium on VLSI Technology and Circuits (VLSI) 2026.
[4] S. G. Kirtania, O. Phadke, E. Sarker, K. A. Aabrar, D. Chakraborty, F. Waqar, S. Jaewon, T. Pantha, S. Dutta, A. I. Khan, S. Yu, S. Datta, “Amorphous indium oxide channel FeFETs with write voltage of 0.9V and endurance >1012 for refresh-free 1T-1FeFET embedded memory,” IEEE International Electron Devices Meeting (IEDM) 2024.
[5] X. Wu, A.I. Khan, H. Lee, C.-F. Hsu, H. Zhang, H. Yu, N. Roy, A.V. Davydov, I. Takeuchi, X. Bao, H.-S.P. Wong, E. Pop, “Novel Nanocomposite-Superlattices for Low Energy and High Stability Nanoscale Phase-Change Memory,” Nature Commun. 15, 13 (2024).
[6] J. Lee, C. Zhang, S. Park, H. Park, T.-H. Kim, L. J.-C. Liu, E. Ambrosi, M. Song, X. Bao, M.-F. Chang, S. Datta, S. Yu, “Monolithic 3D integration of dual-gated ALD oxide-channel non-volatile capacitive memory on 40nm Si CMOS for digital compute-in-memory,” IEEE International Electron Devices Meeting (IEDM) 2025.

* “Theme 3 has also demonstrated an nvCap-based Ternary Content-Addressable Memory (TCAM) array enabling charge-domain in-memory search for Hyper-Dimensional (HD) computing, with more than 40× improvement in search energy–delay product relative to conventional 16-transistor TCAM designs [7]”

References: 

[7] O. Phadke, J. Lee, P.-K. Hsu, C. Zhang, A. I. Khan, S. Datta, S. Yu, “Array-level demonstration of charge-domain in-memory search using back-end-of-line compatible ferroelectric nonvolatile capacitors,” IEEE International Electron Devices Meeting (IEDM) 2025.

* “Besides, Theme 3 has explored exploratory two-dimensional materials as channel materials for access transistors along vertical sidewalls, including a vertical NAND prototype using a monolayer MoS₂ channel.”

* “Another notable strength of Theme 3 is its close integration with other research themes within PRISM. PRISM researchers completed the integration of the NeuroSim-Cache tool [8] with architectural simulators such as gem5, enabling emerging memory technologies to be evaluated within CPU, GPU, and FPGA system contexts”

References:

[8] F. G. Waqar, J. Kwak, J. Lee, O. Phadke, M. Shon, M. Gholamrezaei, K. Skadron, S. Yu, “Optimization and benchmarking of monolithically stackable gain cell memory for last-level cache,” IEEE Transactions on Computers, vol. 75, no. 3, pp. 760-775, 2026.