High-level specification to chip: SPIRAL-generated logic-to-tapeout FFT accelerator (radix-4 and radix-8)
PI Priyanka Raina
Opal: Next generation AIMS data processor for sparse machine learning
PI Tajana Rosing & PI Mingu Kang
40nm ReRAM HDnn – Few shot learning for ImageNet with analog ReRAM PIM; Collaboration with Prof. Gert Cauwenberghs@UCSD, Carlos Diaz & Leo Liu @TSMC
PI Tajana Rosing & PI Mingu Kang
40nm ASIC HDnn – Few shot learning for ImageNet with low-power feature extractor via pattern sharing; Collaboration with Carlos Diaz & Leo Liu @TSMC; [ESSCIRC24]
PI Mingu Kang
65nm L1 / dot product dual kernel reconfigurable AI processor with PE-level fine-grain power gating
[under review in JSSC]
Collaboration with Samsung
PI Mingu Kang
65nm analog PIM and digital hybrid processor for attention accelerator via token pruning for transformers [ESSCIRC24]
Collaboration with Samsung
PI MinguKang & Tajana Rosing
65nm XGBoost tree-based ensemble classifier with modular tree units and reconfigurable interconnects [CICC24]
PI Shimeng Yu
Compute in memory in two different modes on GF 28nm FeFET: drain current & capacitive sensing modes; 3x compute & 8x energy efficiency of ReRAM CIM
PRISM 2024 Devices Gallery
PI H.-S. Philip Wong
Edge Continual Training and Inference with RRAM-Gain Cell Memory Integrated on Si CMOS [IEDM’24]
PI H.-S. Philip Wong
First Experimental Demonstration of Hybrid Gain Cell Memory with Si PMOS and ITO FET for High-speed On-chip Memory [VLSI’24]
PI H.-S. Philip Wong
Chip Micrograph of Complementary Gain Cell fabricated at Stanford in collaboration with TSMC
PI Eric Pop
PCM based on TiTe2/Ge4Sb6Te7 superlattice used in HD computing for mass spectrometry data analysis [IEEE JxCDC’24]
PI SayeefSalahuddin
Enhanced Spin Hall Conductivity in Metal/Semimetal Heterostructure for Energy-efficient Magnetic Memory
PI Vijay Narayanan & PI Kai Ni @ SUPREME
Successful integration of the vertical 2T-3C FeRAM cell by stacking the vertical metal-ferroelectricmetal stack on top of CMOS transistors; quasi-nondestructive read out without write back after 10^6 reads
PI Vijay Narayanan & Shimeng Yu PI Kai Ni & M. Namier @ SUPREME
Charge Domain Compute-in-Memory Array with Binary and MLC FeFET;
3200 TOPS/W; 231.67 TOPS/mm2 with 1-bit input and 1-bit weight operations
PI Suman Datta
GAA AOS NSFETs (based on W-doped In2O3) used as access transistors for monolithic 3D DRAM [IEDM ’24]
PI Suman Datta, PI Shimeng Yu, Asif Khan @ SUPREME
Enlarging the MW for Fe-VNAND to 7~8V to allow TLC operation
PRISM 2023 Chips & Devices Gallery
PI Shimeng Yu
Courtesy 300mm wafer from Global Foundries 28nm FeFET process for nvCap characterization ( with GF Dresden team)
PI Shimeng Yu
1st gen FeFET PIM macro in GF 28SLPe shuttle via Fraunhofer IIS MPW shuttle w/ FeFET risk manufacturing
PI Tajana Rosing
40nm ASIC & ReRAM HDnn – Few shot learning for ImageNet size images
Collaboration with TSMC
PI Priyanka Raina
First AIMS data processor for programmably accelerating both dense and sparse applications
PI Philip Wong
Oxide Semiconductor Gain Cell fabricated at Stanford
PI Datta
Chip micrograph of asymmetric dual-gate (ADG) Ferroelectric memory cell array
PI Pop
Superlattice phase change memory fabricated at Stanford University
PI Salahuddin
Top view of 3D Interlayer-Exchange-Coupled Memory Devices